Cursor Masked Interrupt Status register
| CRSRMIS | Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |